ASIC Design Verification Engineer

Broadcom

ASIC Design Verification Engineer developing silicon products for Ethernet systems in the Cloud. Creating devices that accelerate AI/ML workflows with a skilled team.

Posted 6/18/2026full-timeIrvine • California, Colorado, Massachusetts • 🇺🇸 United StatesSeniorLead💰 $129,400 - $207,000 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM.
Work with worldwide design and architecture teams to develop leading edge products.
All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Requirements

What you’ll need

Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience
Constrained random verification methodologies with experience driving completion via coverage closure.
Preferable to have skills with SV and UVM, well versed in OOP Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)

Benefits

Comp & perks

Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
company paid holidays
paid sick leave and vacation time.

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

System VerilogUVMconstrained random verificationcoverage closureobject-oriented programmingVCSIncisivescriptingPythonPerl

Soft Skills

technical leadership

Certifications

Bachelor's degreeMaster's degreePhD