Digital Design RTL Engineer

Broadcom

Digital Design RTL Engineer developing high-quality SystemVerilog RTL for semiconductor solutions. Collaborating with teams for project milestones while ensuring timing closure and design hand-off.

Posted 5/14/2026full-timeFort Collins • California, Colorado • 🇺🇸 United StatesMid-LevelSenior💰 $91,000 - $146,000 per yearWebsite

About the role

Key responsibilities & impact

Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule

Requirements

What you’ll need

BSEE required, MSEE/PhD preferred
5+ years of industry experience with a focus on SoC integration, LPDDR5/6, DDR4/5 and/or high-speed SerDes, or HBM protocols is highly preferred
High proficiency in SystemVerilog
Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below)
Deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques

Benefits

Comp & perks

Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SystemVerilogRTL designPPA optimizationclock domain crossing analysislow-power design techniquesSoC integrationLPDDR5LPDDR6DDR4DDR5

Soft Skills

autonomycollaborationrisk mitigationproject management

Certifications

BSEEMSEEPhD