Join a high performance design team responsible for state-of-the-art subsystem development
Verification environment development using modern verification techniques (System Verilog and UVM)
Designing verification components such as UVM agents and behavioral models
Implementing coverage and assertions using System Verilog
Developing random & directed test cases against the specification
Analyzing and debugging simulation failures
Analyzing coverage results

Requirements

Bachelors in EE, CE, or CS with 12+ years of related experience OR Masters degree in EE, CE, or CS with 10+ years of related experience
Working in SoC and IP development programs
Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog
Expertise in designing in constrained random environments using UVM, OVM, or VMM.
Experience running and debugging using HDL simulators
Demonstrated familiarity with OOP languages (C++, Java, etc.)
Proficient with OOP techniques

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

System VerilogUVMVerilogVHDLHDL simulatorsOOPC++Javaconstrained random environmentstest case development

Certifications

Bachelors in EEBachelors in CEBachelors in CSMasters in EEMasters in CEMasters in CS