Lead ASIC - FPGA Design Engineer

Boeing

Lead FPGA Design Engineer at Boeing India overseeing end-to-end FPGA designs for aerospace systems. Collaborating with teams, defining methodologies, and managing project risks in hybrid working environment.

Posted 7/20/2026full-timeBangalore • 🇮🇳 IndiaSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in FPGA/SoC design, RTL development using Verilog/SystemVerilog, and high-speed interface design. Proven ability to lead teams, manage risks, and ensure compliance with industry standards such as DO-254.

Highest-signal resume keywords

FPGA Architecture DevelopmentRTL Design Using Verilog/SystemVerilogHigh-Speed Interface DesignFPGA Tools: Xilinx Vivado, Intel QuartusDigital ASIC/FPGA Requirements Specification

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

RTL DesignSynthesisPlace & RouteTiming ClosureStatic Timing AnalysisCode Coverage AnalysisClock Cross Domain AnalysisDigital ASIC/FPGA DesignTestbench DevelopmentProblem Solving

Soft Skills

LeadershipAnalytical ThinkingCommunicationOwnershipCollaboration

Tools & Technologies

Version Control Systems: SVN, CVS, GitFPGA Tools: Xilinx VivadoFPGA Tools: Intel Quartus

Industry Keywords

DO-254KPI MeasuresSupplier ManagementDesign MethodologiesBest Practices

Tech Stack

Tools & technologies

Subversion

About the role

Key responsibilities & impact

Lead complex FPGA/SoC design from concept to production.
Own FPGA Architecture development and design strategy across the projects.
Define FPGA design methodologies, coding standards and best practices.
Lead the RTL development (using Verilog / SystemVerilog) efforts.
Lead and mentor a team of FPGA engineers, drive design reviews and help in capability building.
Proactively manage risks, dependencies and plan effective mitigations.
Demonstrates problem solving skills to resolve technical issues on architectural approaches, requirements, specifications and design.
Drives the design quality, KPI measures, documentation and compliance to industry standards such as DO-254 (DAL A/B/C/D as applicable) or equivalent.
Leads activities in support of Supplier Management with make/buy recommendations and other technical services.
Effectively collaborate with cross functional teams and leadership.
Evaluates and integrates third-party IP and verification IP (VIP).
Stay ahead on new technologies and standard processes.
Deliver upon Stage Gate Reviews, establish processes and drive design excellence.
Conducts technical training, allocates tasks, review deliverables and ensures productivity.
Possess strong ownership and accountability, has ability to influence and drive technical decisions.
Excellent problem-solving, analytical thinking and communication skills.
Coordinates engineering support throughout the lifecycle of the product.
Plans research projects to develop concepts for future product designs to meet projected requirements.
Works under minimal direction.

Requirements

What you’ll need

Bachelor degree in Engineering, Engineering Technology (including Manufacturing Technology), Electronics, Electrical, Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications directly related to the work statement.
Proven experience in RTL design using Verilog/System Verilog and perform synthesis, place & route, timing closure and optimization.
Experience on high-speed interfaces design such as PCIe, DDR, Ethernet, SerDes, etc.
Proven experience in designing digital ASIC/FPGA architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
Experience deriving digital ASIC/FPGA requirements specification from higher-level (system or board-level) requirements specifications.
Experience in designing robust testbench and performing code coverage analysis.
Work experience performing RTL synthesis, clock cross domain analysis (CDC), Static Timing Analysis and correcting timing violations.
Experience using Version Control Systems: Subversion (SVN), CVS, Git or equivalent.
Support hardware and software teams in board bring-up, debugging & troubleshooting activities, and system level issues resolution.
FPGA Tools: Xilinx Vivado, Intel Quartus or equivalent.

Benefits

Comp & perks

Flexible work arrangements
Professional development opportunities