Summer Intern, Validation Engineer
Cirrus Logic
LinuxShell ScriptingUnix
ASIC/FPGA Design and Verification Engineer – Lead, Senior or Principal
Boeing
full-time
Posted on:
Origin: • 🇺🇸 United States • Washington
Visit company websiteSalary
💰 $126,650 - $257,600 per year
Job Level
Senior
Tech Stack
LinuxPerlPythonSubversion
About the role
- Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams, and manage team execution to meet program milestones
- Collaborate with customers, system engineers, and hardware engineers to capture requirements and architect digital logic functions
- Explore trade-space of potential ASIC/FPGA technologies and determine optimal parts considering Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
- Implement FPGA/ASIC from block-level micro-architecture, through HDL coding, to physical design realization (through gate-level netlists for ASICs)
- Integrate DSP IP and third-party IP as needed
- Perform static timing analysis, LEC, CDC, linting, and other necessary checks
- Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
- Create self-checking and reusable test benches using OOP concepts and leverage UVM components
- Drive FPGA-based prototyping and validation; validate design through hardware integration test with special test equipment and test-beds
- Train and mentor less senior engineers and help build effective project teams
Requirements
- Bachelor of Science degree in engineering, engineering technology, chemistry, physics, mathematics, data science, or computer science (or equivalent)
- 5+ years of ASIC/FPGA design or verification experience
- Experience with ASIC/FPGA architectural definition and detailed design implementation
- Functional verification using SystemVerilog and delivery/release of production designs
- Professional experience with hardware-based integration and test of ASIC/FPGA designs
- Proven record of leading ASIC/FPGA design and/or verification teams and reporting progress to stakeholders
- Ability to perform static timing analysis, LEC, CDC, linting, and other checks
- Experience developing Functional Coverage Models and closing Code Coverage
- Ability to create self-checking and reusable testbenches from scratch using OOP concepts and UVM
- Experience with FPGA-based prototyping and hardware integration test
- Ability to collaborate with customers, system engineers, and hardware engineers
- Must meet export control compliance: U.S. Person required as defined by 22 C.F.R. §120.15
- Ability to obtain U.S. Security Clearance (U.S. Citizenship required for clearance)
- Employer will not sponsor applicants for employment visa status
- Post-offer drug testing in accordance with company policy
- Preferred: 10+ years related experience or advanced degree; Master’s or equivalent experience
- Preferred: experience with hardware emulators (especially Palladium), SystemVerilog Assertions, executable test plans
- Preferred: proficiency in OOP concepts, high-speed SerDes interfaces (JESD204C, PCIe, Ethernet)
- Preferred: scripting (Make, Perl, Python), revision control (svn, cvs, git), Linux environments
- Preferred: familiarity with space-based design techniques and radiation mitigation
- Preferred: demonstrated history of 1st pass success with ASIC designs
