Senior Design Engineer

AccelerComm Ltd

Senior Design Engineer responsible for ASIC/FPGA design in non-terrestrial communications technology. Collaborating with teams to develop cutting-edge 5G solutions for satellite communication.

Posted 7/15/2026full-timeSouthampton • 🇬🇧 United KingdomSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expert knowledge in RTL languages such as Verilog and SystemVerilog for ASIC and FPGA designs, with a strong focus on optimization techniques for high throughput data processing. Proficient in collaborating across teams to deliver integrated solutions while adhering to established engineering methodologies.

Highest-signal resume keywords

Expert Knowledge Of RTL LanguagesDigital Design Delivery In ASIC And FPGAEDA Tools For Simulation And SynthesisCommunications Signal Processing AlgorithmsUVM Verification Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

VerilogSystemVerilogC++SystemCTiming AnalysisPower Management TechniquesHigh Speed InterfacesScripting Language (Python)ASIC DesignFPGA Design

Soft Skills

CollaborationTechnical Documentation Writing

Tools & Technologies

EDA ToolsFPGA Development PlatformsAMD FPGAsDesign Tools

Industry Keywords

Micro-ArchitectureDesign FlowAgile MethodologyWaterfall MethodologyAMBA Bus Protocols

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
Deploy your designs onto the latest FPGA development platforms for validation and system integration
Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA

Requirements

What you’ll need

Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
A strong skillset in delivering digital designs in the ASIC and FPGA industry
Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
Track record in collaborating across teams to produce integrated solutions
Experience in technical documentation writing – design specifications, user guides, verification plans
Expert user of EDA tools for simulation and synthesis
Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
Familiarity with the AMBA bus protocols
Understanding of UVM verification techniques or practical experience using UVM for IP verification
Experience using C++/SystemC for design modelling and integration
Experience with high speed interfaces such as PCI-E or JESD
Knowledge of a scripting language, such as Python
Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools

Benefits

Comp & perks

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