Hardware Engineer

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams.
• Play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Craft solutions and debug with minimal mentorship.

ASIC DFT Engineer – 8+ years – DFT, ATPG, MBIST, SCAN, JTAG

• Design and build hardware platforms optimized for AI training and inference workloads.
• Evaluate, integrate, and validate servers, GPUs, networking equipment, storage systems, and accelerator hardware.
• Develop scalable hardware architectures supporting enterprise AI deployments across cloud, hybrid, and on-premises environments.
• Collaborate with software and platform engineering teams to optimize hardware and software integration.
• Optimize compute, memory, storage, networking, and GPU performance for AI workloads.
• Benchmark and analyze system performance under production-scale AI deployments.
• Identify hardware bottlenecks and implement improvements to maximize throughput, latency, and infrastructure efficiency.
• Validate hardware compatibility across multiple AI frameworks and deployment environments.
• Build reliable and fault-tolerant hardware infrastructure capable of supporting mission-critical AI workloads.
• Develop hardware validation, diagnostics, stress testing, and failure analysis processes.
• Support hardware lifecycle management including provisioning, upgrades, maintenance, and replacement strategies.
• Collaborate with vendors and partners to evaluate emerging hardware technologies.
• Support hardware deployment across enterprise customer environments and internal infrastructure.
• Develop automation and operational procedures for hardware provisioning, monitoring, and troubleshooting.
• Ensure infrastructure meets enterprise standards for availability, security, and operational excellence.
• Work closely with customer-facing teams to resolve deployment and infrastructure challenges.
• Establish best practices for hardware validation, documentation, testing, and operational readiness.
• Conduct technical reviews and contribute to infrastructure architecture decisions.
• Collaborate across hardware, software, platform, and AI engineering teams to continuously improve system performance and reliability.

• Analysis of requirements, creating hardware designs, implementation, testing and documentation of automotive hardware components
• Quality of Hardware deliverables and their reviews
• Electronics Hardware design during entire hardware development life cycle
• Technical mentoring of Hardware team

Hardware Architect

• Own and define/participate in end-to-end validation strategy for coherent pluggable optics and transponder products features, ensuring carrier-class quality.
• Drive system-level, feature-level, and regression test planning aligned with product architecture, standards, and customer use cases.
• Lead and execute complex validation using white-box and black-box testing across HW, ASIC, FW, and SW layers..
• Collaborate closely with HW, Optical, ASIC, FW, and SW teams to influence design for testability.
• Lead root cause analysis (RCA) of customer-found and field issues; enhance test coverage to prevent recurrence.
• Participate in the test automation strategy and roadmap, ensuring scalability and long-term maintainability.
• Ensure validation readiness, quality metrics, and release sign-off with clear risk assessment.

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ASIC DFT Engineer – 8+ years – DFT, ATPG, MBIST, SCAN, JTAG

Hardware Engineer

Hardware Architect

Senior Firmware Engineer