Mechanical Engineer

• Responsible for the physical design of CPU on-chip interconnect network and last-level caches.
• Work on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility.
• Liaison between Logic design and Physical design teams responsible for achieving timing, area, performance and power goals of the unit.
• Help define the architecture for next-generation Nvidia coherent interconnects and system-level caches.

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