Mechanical Engineer

• Perform physical layout for custom embedded SRAM structures in state-of-the-art FinFET and gate-all-around technologies using Cadence tools
• Floor planning, custom layout, and verifying layout design rules and transistor-level schematics
• Verify the robustness of your layout from a performance and reliability perspective
• Communicating with P&R teams to determine optimal interface specifications between custom layout and standard cell-based logic
• Lead and mentor other mask designers to improve team efficiency and align design methodologies

Senior Layout Mask Design Engineer

Senior Board Design Engineer

Product Design Engineer

Photonics Design Engineer

Manager, Product Design Engineering

PCB Design Engineer, Level 5