• work with a global team on the physical design of complex chips
• triage workflows
• run RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip
• analyze performance by running timing analysis
• verify a robust power grid by performing EMIR analysis
• review completed runs for errors or create optimizations from successful runs

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or equivalent work experience
Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (7nm, 5nm, or below)
Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, Synopsys Design Compiler, IC Compiler and Fusion Compiler
Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
Enjoy learning by doing the work and having access to guides and a mentor
Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before

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Hard Skills

physical design
RTL code synthesis
place and route (PnR)
timing analysis
EMIR analysis
block-level PNR
static timing analysis
physical verification
formal verification

Soft Skills

team collaboration
problem-solving
willingness to learn
initiative

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