SDET

• work with a high-performing DFT/DV team within a DFT organization
• design verification, at block and full-chip, of DFT IP inserted at RTL level
• UVM test case development when new DFT RTL is added into a design
• gain experience in DFT architecture given the requirement that underlying logic be thoroughly tested in RTL form
• opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files
• work with JTAG, 1687, and evolving chiplet to chiplet test busses
• use of Siemens EDA tools to insert scan and memory BIST, and the verification of these inserted test elements

Design for Test Engineering Intern – Bachelors Degree

Senior Manager, Software Test Engineering – Hybrid

Senior Manager, Software Test Engineering – Web Applications

Senior Software Development Engineer in Test – Hybrid

Senior Software Test Engineer

Senior Software Test Engineer