Engineer

• Own validation strategy, test planning, and execution for PCIe, CXL, and UALink across silicon, platform, rack, and cluster configurations
• Develop comprehensive validation coverage for link training, error handling, fabric scaling, congestion, performance, and protocol compliance
• Perform bring-up and debug of high-speed I/O subsystems using protocol analyzers, exercisers, and signal measurement tools
• Validate interconnect behavior under AI/ML workloads, stress conditions, and multi-node traffic patterns
• Drive interoperability testing across GPUs, accelerators, switches, storage, and memory devices from diverse ecosystem partners
• Collaborate with silicon design, board design, firmware, and software teams to resolve complex cross-layer issues
• Build automation, diagnostics, and scaling frameworks to validate fabrics at rack-level and multi-rack cluster scale
• Analyze performance metrics, identify bottlenecks, and recommend architectural or firmware tuning for optimal interconnect efficiency
• Influence next-generation high-speed I/O roadmap by providing data-driven insights from validation cycles
• Engage with hyperscalers, OEMs/ODMs, and industry partners to ensure end-to-end readiness for deployment

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