Senior Microelectronics Engineer
Telespazio Belgium
Python
Intern, RISC-V Architecture Evaluation and Co-Design
Factorial
internship
Posted on:
Origin: • 🇪🇸 Spain
Visit company websiteJob Level
Entry Level
Tech Stack
Python
About the role
- Evaluate Openchip RISC-V platforms for performance, power efficiency, and scalability using HLRS workloads
- Plan and execute controlled benchmarks on RISC-V boards, simulators, and FPGA prototypes
- Analyze strong/weak scaling, bandwidth sensitivity, cache/NUMA effects, and vector/ISA utilization
- Model energy-to-solution and performance per watt and compare against established baselines
- Optimize kernels via compiler flags, vectorization, and memory placement; quantify gains
- Produce a prioritized co-design brief (ISA/runtime/compiler/hardware) backed by evidence
- Collaborate virtually with HLRS for workload curation and validation; optional short visits to Openchip
Requirements
- Pursuing MSc in Computer Science, Computer Engineering, Electronics Engineering, or related field
- Proficient in C/C++ and Python; comfortable with build systems and benchmarking
- Knowledge of performance analysis (roofline, CPI stacks, Amdahl/Gustafson)
- Familiarity with MPI/OpenMP and systems fundamentals
- Strong technical writing for reproducible reports
- Preferred: RISC-V ISA (incl. Vector) and LLVM/GCC toolchains
- Preferred: Autotuning, kernel optimization, or numerical libraries experience
- Preferred: gem5, RTL/FPGA flows, or basic power/perf modeling
- Preferred: Track record of patches/RFCs/spec proposals
