Architect

• Evaluate Openchip RISC-V platforms for performance, power efficiency, and scalability using HLRS workloads
• Plan and execute controlled benchmarks on RISC-V boards, simulators, and FPGA prototypes
• Analyze strong/weak scaling, bandwidth sensitivity, cache/NUMA effects, and vector/ISA utilization
• Model energy-to-solution and performance per watt and compare against established baselines
• Optimize kernels via compiler flags, vectorization, and memory placement; quantify gains
• Produce a prioritized co-design brief (ISA/runtime/compiler/hardware) backed by evidence
• Collaborate virtually with HLRS for workload curation and validation; optional short visits to Openchip

Intern, RISC-V Architecture Evaluation and Co-Design

Senior System Architect – Pega Certified

Arquitecto/a Responsable de Proyectos

Integration Architect

Arquitecto de Integración

Arquitecto/a Cloud – 100% Teletrabajo